The present invention relates generally to a power up reset (PUR) circuit that generates a reset pulse during a power up operation to reset components, such as flip-flops, latches and registers, in an integrated circuit (IC).
A PUR circuit can bring an IC into a well-defined state before normal operation. The power up reset sequence brings the IC to this state by resetting the system components with pulses generated by the circuit, such that the device will function properly.
Conventional PUR circuit designs are based on a time-triggered system controlled by the charging and discharging time of capacitors. While the system can provide the pulse needed, the circuit may fail when the RC time constants are much faster than the ramp-up time of the supply voltage. Unlike devices with higher supply voltage, the ramp-up rate for a low voltage circuit is slow, and conventional PUR circuit designs often encounter problems when dealing with such slow ramp-up rate. The ramp-up rate of supply voltage in low power circuits can be 1 ms to 10 ms or even slower. As technology continues to improve and low voltage processes are becoming more common, solutions to such a problem are needed. In order for a conventional PUR circuit to function properly at such a slow ramp-up rate, large capacitors or other MOS devices may need to be implemented to increase RC time constants. However, such components will enlarge the circuit, thereby making the circuit impractical.
An ideal PUR circuit should provide a consistent pulse generation at any ramp-up rate, while consuming zero DC current. The ideal PUR circuit should also occupy a small area for practical purposes.
It is desirable in the art of power up reset circuits to have new designs that are not based on triggering by the charging and discharging time of capacitors and reduced in circuit area.